1. Field of the Invention
The present invention generally relates to a controller for a semiconductor memory device and a system comprised of a semiconductor memory device and a controller. The present invention particularly relates to a controller for a semiconductor memory device that outputs data of a double data rate together with a strobe signal, and relates to a system that controls data of a double data rate by a strobe signal.
2. Description of the Related Art
Semiconductor memory devices such as DRAMs that operate at a double data rate generally output data signals and a data strobe signal at the same phase timing, and keep data changes of the data signals at the same timing as the rising edges and falling edges of the strobe signal. A controller that is connected to a semiconductor memory device receives the strobe signal, and delays it by a proper time length. The controller takes in the data by latching the data signals by use of the delayed strobe signal.
In the controller, a delay circuit comprised of a series of inverters or the like is used to delay the strobe signal, thereby generating a timing signal for latching the data signals at optimum timing. If the delay of the delay circuit changes because of variation of manufacturing processes, fluctuation of ambient temperature or power supply voltages, etc., it would be difficult to maintain optimum timing for data acquisition. Namely, it would be difficult to maintain a proper data-hold time and a proper data-setup time for data acquisition.
Accordingly, there is a need for a controller connected to a semiconductor memory device wherein the controller can maintain optimum data acquisition timing even in the presence of various factors for timing fluctuation.
It is a general object of the present invention to provide a memory controller that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.
It is another and more specific object of the present invention to provide a memory controller connected to a semiconductor memory device wherein the controller can maintain optimum data acquisition timing even in the presence of various factors for timing fluctuation.
In order to achieve the above objects according to the present invention, a memory controller for controlling a memory that is connected thereto and outputs data of a double data rate together with a strobe signal includes a clock signal generation circuit which generates a clock signal supplied to the memory, and a data acquisition circuit which delays the strobe signal through feedback control that makes a delay substantially equal to a xc2xc cycle of the clock signal, and which latches the data in response to a timing signal that is the delayed strobe signal.
In the memory controller as described above, the timing signal used for the latching of the data is the delayed strobe signal that is delayed by a xc2xc cycle of the clock signal, so that the data signal is latched at an exact midpoint between data change timings of the data signal, thereby providing an optimum data-hold time and an optimum data-setup time. Further, since the delay is not provided as a fixed predetermined delay, but is controlled through feedback control to be a xc2xc cycle of the clock signal, an optimum data acquisition timing is insured even in the presence of various variation factors such as variation of the manufacturing process, variation of ambient temperature, variation of a power supply voltage, etc. Moreover, the circuit size of the data acquisition circuit can be reduced by using an inverse of the clock signal and/or a signal having double a frequency of the clock signal as a reference signal for the feedback control.
Further, a system comprised of the memory controller as describe above and the memory of a double data rate can attain the same advantages as described above.
According to another aspect of the present invention, a memory system includes a memory device which outputs a strobe signal, and outputs data in synchronization with the strobe signal, a memory controller which includes a variable delay circuit that generates a latch signal by delaying the strobe signal, and latches the data in synchronization with the latch signal, and a delay selection unit which successively reads reference data of a given data value from the memory device while successively changing a delay of the variable delay circuit, and checks whether a value of the successively read reference data matches the given data value so as to obtain a range of the delay within which proper read operation is performed, thereby selecting the delay of the variable delay circuit based on the obtained range.
According to the memory system described above, a range of the delay of the variable delay circuit is obtained that allows data to be properly latched during an actual read operation, and the delay is set to an optimum delay within the obtained range, so that the memory system of the present invention can cope with any clock cycles, and is capable of a latch operation of optimum timing even if there is manufacturing variation, temperature variation, power-supply-voltage variation, etc. Further, since a plurality of variable delay circuits are not necessary, a simple circuit structure suffices to achieve its purposes. Moreover, the minimum adjustable delay of the variable delay circuit is equal to the delay of one delay stage, so that fine adjustment is possible despite the use of a simple circuit structure.
Further, the delay selection unit may be implemented as a microprocessor connected to the memory controller and a program executed by the microprocessor. This provides a simple configuration that can be readily achieved.
Moreover, the delay selection unit may be provided with a register that stores therein the reference data, which is written in the memory device via the memory controller, followed by being read from the memory device. Since the reference data is stored in the register, all that is necessary to check whether a proper read operation is performed is to compare the reference data read from the memory device with the data of the register.
The delay selection unit as described above may set the delay at the midpoint of the obtained range within which data can be properly latched. Further, the delay of the variable delay circuit is selected at a time of power-on of the memory system, and is maintained thereafter. Since there is a possibility that the delay deviates from the optimum delay as time passes, the delay of the variable delay circuit is selected at constant intervals, and is maintained until the next setting operation.